This invention relates to a semiconductor memory device and a method for accessing the same and more particularly to a memory to which serial access is made.
Conventionally, a serial access memory is manufactured as an inexpensive semiconductor memory device. FIG. 1 is a circuit diagram showing an extracted portion of a circuit associated with access to memory cells in a serial access type mask ROM used as one example of this type of semiconductor memory device. In a memory cell array 11, memory cells MC, MC, . . . are arranged in a matrix form. The memory cells MC, MC, . . . are disposed in intersecting positions between word lines WL, WL, . . . extending in a row direction and bit lines BL, BL, . . . extending in a column direction. The gates of the memory cells MC, MC, . . . on the same row are connected to a corresponding one of the word lines WL, WL, . . . , the drains thereof on the same column are connected to a corresponding one of the bit lines BL, BL, . . . and the sources thereof are connected to a ground node. Data is programmed into the memory cells MC, MC, . . . by use of a photomask in the manufacturing process by forming a MOS transistor or not, forming a depletion type MOS transistor or enhancement type MOS transistor, or forming a contact hole or not according to storage data of "0" or "1" Sense amplifiers (S/A) 12, 12, . . . are respectively connected to the bit lines BL, BL, . . . A row decoder 13 decodes a row address signal RAdd to selectively drive the word lines WL, WL, . . . A circuit portion of the row decoder 13 which corresponds to one word line WL is constructed by a NAND gate and an inverter for inverting the output signal of the NAND gate, for example. A column decoder 14 decodes an output signal of a column address counter 15 to selectively control the ON/OFF states of column selection transistors 16, 16, . . . A circuit portion of the column decoder 14 which corresponds to one column selection transistor 16 is constructed by a NAND gate and an inverter for inverting the output signal of the NAND gate, for example. The column address counter 15 is supplied with a column address signal CAdd, address latch enable signal ALE and read signal RD. One-side ends of the current paths of the column selection transistors 16, 16, . . . are respectively connected to the output terminals of the sense amplifiers 12, 12, . . . and the other ends thereof are commonly connected to the input terminal of an output buffer 17. The read signal RD is input to the output buffer 17 which in turn outputs read out data D.sub.OUT from a selected memory cell MC.
FIG. 2 is a timing chart for schematically illustrating the readout operation of the mask ROM shown in FIG. 1. An address input A.sub.IN (containing the row address signal RAdd and column address signal CAdd) is supplied to the column address counter 15 and row decoder 13 in response to the down-edge of the address latch enable signal ALE. The row address signal RAdd is decoded in the row decoder 13 and the word lines WL, WL, . . . are selectively driven according to the decoded output. Since the memory cells MC, MC, . . . on the same row are connected to a corresponding one of the word -lines WL, WL, . . . , the row of the memory cells MC, MC, . . . in the memory cell array 11 are selected by the row decoder 13.
The column address signal CAdd is set in the column address counter 15 as an initial value and the count value of the counter 15 is supplied to and decoded by the column decoder 14. After the word line WL is selected by the row decoder 13, the column address counter 15 effects the count-up operation in synchronism with the read signal RD. A decoded output signal of the column decoder 14 is supplied to the gates of the column selection transistors 16 , 16, . . . to sequentially control the ON/OFF states of the transistors 16, 16, . . . . Storage data items of the memory cells MC, MC, . . . of one row connected to the word line WL driven by the row decoder 13 are respectively read out on the bit lines BL, BL, . . . , supplied to the sense amplifiers 12, 12, . . . and sensed and amplified by the sense amplifiers. Then, data is supplied to the output buffer 17 via the column selection transistor 16 selected by the column decoder 14 and output as read out data D.sub.OUT. The output operation of the output buffer 17 is controlled by the read signal RD and read out data items D.sub.OUT of the address N, address (N+1), address (N+2) . . . are serially output in response to the read signal RD.
Since the conventional serial access memory described above has the sense amplifiers 12 , 12, . . . provided for the respective bit lines BL, BL, . . . and the number of sense amplifiers is large, there occurs a problem that the power consumption is high and the chip size becomes large. In addition, the memory cell of the mask ROM is formed of one transistor, but the sense amplifier 12 requires at least 6 transistors, and it becomes more difficult to dispose the sense amplifier 12 in a pitch between the memory cells MC and MC as the memory cell size becomes smaller, thereby making it extremely difficult to make the appropriate layout of the sense amplifiers 12, 12, . . . .